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cy7c197bn 256-kb (256 k 1) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06447 rev. *c revised april 6, 2011 256-kb (256 k 1) static ram features fast access time: 15 ns wide voltage range: 5.0 v 10% (4.5 v to 5.5 v) cmos for optimum speed and power ttl compatible inputs and outputs available in 24-pin dip and 24-pin soj general description [1] the cy7c197bn is a high performance cmos asynchronous sram organized as 256 k 1 bits that supports an asynchronous memory interfac e. the device features an automatic power down feature that significantly reduces power consumption when deselected. see the truth table on page 8 for a complete description of read and write modes. the cy7c197bn is available in 24-pin dip and 24-pin soj package(s). note 1. for best practice recommendations, refer to the cypress application note system design guidelines on www.cypress.com . row decoder column decoder input buffer sense amps a x x dout we ce din power down circuit ram array logic block diagram product portfolio description -15 -25 unit maximum access time 15 25 ns maximum operating current 150 95 ma maximum cmos standby current 10 10 ma [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 2 of 13 contents pin layout and specification ......................................... 3 pin description ................................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 4 ac test loads .................................................................. 5 ac test conditions .......................................................... 5 ac electrical characteristics .......................................... 6 timing waveforms ........................................................... 6 read cycle no. 1 ........................................................ 6 read cycle no. 2 ........................................................ 7 write cycle no. 1 (we controlled) .............................. 7 write cycle no. 2 (ce controlled) ............................... 8 truth table ........................................................................ 8 ordering information ........................................................ 9 ordering code definitions ..... ...................................... 9 package diagrams .......................................................... 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 3 of 13 pin layout and specification pin description pin type description dip soj a x input address inputs 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23 ce control chip enable 13 13 din input data input pins 14 14 dout output data output pins 10 10 v cc supply power (5.0 v) 24 24 we control write enable 11 11 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 dout we gnd ce din a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 24-pin dip (6.6 31.8 3.5 mm) a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 dout we gnd ce din a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 24-pin soj (8 15 3.5 mm) [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 4 of 13 maximum ratings exceeding the maximum rating may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage on v cc to relative gnd ......?0.5 v to +7.0 v dc voltage applied to outputs in high z state [2] .................................. ?0.5 v to v cc + 0.5 v dc input voltage [2] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low)..... .................................... 20 ma static discharge voltage...............................................2001 v (per mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range range ambient temperature [3] v cc commercial 0 c to 70 c 5.0 v 10% dc electrical characteristics [2] parameter description condition 15 ns 25 ns unit min max min max v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage ?0.3 0.8 ?0.3 0.8 v v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min, l ol = 8.0 ma ? 0.4 ? 0.4 v i oz output leakage current gnd ? vi ? v cc , output disabled ?5 +5 ?5 +5 a i ix input leakage current gnd ? vi ? v cc ?5 +5 ?5 +5 a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc ? 150 ? 95 ma i sb1 automatic ce power down current ttl inputs v cc = max, ce ? v ih , v in ? v ih or v in ? v il , f = f max ? 30 ? 30 ma i sb2 automatic ce power down current cmos inputs v cc = max, ce ? v cc ? 0.3 v, v in ? v cc ? 0.3 v or v in < 0.3 v, f = 0 ? 10 ? 10 ma capacitance [4] parameter description conditions max (all ? packages) unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 8pf c out output capacitance 10 thermal resistance [4] parameter description conditions 24-pin dip 24-pin soj unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 square inches, two-layer printed circuit board 75.69 84.15 c/w ? jc thermal resistance (junction to case) 33.80 37.56 notes 2. v il (min) = ?2.0 v for pulse durations of less than 20 ns. 3. t a is the ?instant on? case temperature. 4. tested initially and after any design or process change that may affect these parameters. [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 5 of 13 ac test loads [5] note 5. test conditions assume a transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v. v cc v ss rise time 1 v/ns fall time 1 v/ns all input pulses 90% 10% 90% 10% v output r1 r2 c1 cc v output r3 c2 cc r4 output loads output loads t hzce & t hzwe * including scope and jig capacitance (b)* (a)* r th th v thevenin equivalent for ac test conditions parameter description nom. unit c1 capacitor 1 30 pf c2 capacitor 2 5 r1 resistor 1 480 ? r2 resistor 2 255 r3 resistor 3 480 r4 resistor 4 255 r th resistor thevenin 167 v th voltage thevenin 1.73 v [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 6 of 13 ac electrical characteristics [4, 6, 7, 8] parameter description 15 ns 25 ns unit min max min max t rc read cycle time 15 ? 25 ? ns t aa address to data valid ? 15 ? 25 ns t oha data hold from address change 3 ? 3 ? ns t ace ce to data valid ? 15 ? 25 ns t lzce ce to low z 3 ? 3 ? ns t hzce ce to high z ? 5 ? 11 ns t pu ce to power-up 0 ? 0 ? ns t pd ce to power-down ? 15 ? 20 ns t wc write cycle time 15 ? 25 ? ns t sce ce to write end 9 ? 20 ? ns t aw address set-up to write end 10 ? 20 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address set-up to write start 0 ? 0 ? ns t pwe we pulse width 9 ? 20 ? ns t sd data set-up to write end 9 ? 15 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high z ? 7 ? 11 ns t lzwe we high to low z 2 ? 3 ? ns notes 6. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data setup and hol d timing should be referenced to the leading edge of the sig nal that terminates the write. 8. t hzce , t hzwe are specified as in part (b) of the ac test loads [5] on page 5 . transitions are measured 200 mv from steady state voltage. 9. device is continuously selected. ce = v il . 10. we is high for read cycle. timing waveforms read cycle no. 1 [9, 10] address data out previous data valid data valid t rc t aa t oha [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 7 of 13 read cycle no. 2 [11, 12, 13] write cycle no. 1 (we controlled) [11, 14] notes 11. tested initially and after any design or process change that may affect these parameters. 12. we is high in read cycle. 13. address valid prior to or coincident with ce transition low. 14. the minimum write cycle time is the sum of t hzwe and t sd . timing waveforms (continued) address ce data out data valid t rc high z t ace t hzce i cc i sb t pu 50% 50% t pd high z vcc supply current t lzce address data in t wc data valid t sce t sa t aw t pwe t ha t hd t sd data out data undefined high impedance t hzwe t lzwe ce we [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 8 of 13 write cycle no. 2 (ce controlled) [15, 16] timing waveforms (continued) address ce we data in t wc data valid t sce t sa t aw t pwe t ha t hd t sd data out high z notes 15. this cycle is ce controlled. 16. if ce goes high simultaneously with we going high, the output remains in a high impedance state. truth table ce we i/ox mode power h x high z deselect/power-down standby (i sb ) l h data out read active (i cc ) l l data in write active (i cc ) [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 9 of 13 ordering information speed (ns) ordering code package diagram package type operating range 15 cy7c197bn-15vc 51-85030 24-pin soj (8 15 3.5 mm) commercial 25 CY7C197BN-25PC 51-85013 24-pin dip (6.6 31.8 3.5 mm) commercial ordering code definitions please contact local sales representative regarding availability of these parts. temperature range: c = commercial package type: xx = v or p v = 24-pin soj p = 24-pin dip speed: xx = 15 ns or 25 ns bn = 0.25 m technology 97 = 256-kbit density with datawidth 1 bit 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - xx x 7 97 c bn [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 10 of 13 package diagrams figure 1. 24-pin (300-mil) soj, 51-85030 figure 2. 24-pin dip (6.6 31.8 3.5 mm), 51-85013 51-85030 *c 51-85013 *c [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 11 of 13 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable dip dual in-line package soj small outline j-lead sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure ? ohms ns nano seconds vvolts a micro amperes ma milli amperes mm milli meter ms milli seconds mhz mega hertz pf pico farad wwatts % percent c degree celcius [+] feedback
cy7c197bn document #: 001-06447 rev. *c page 12 of 13 document history page document title: cy7c197bn 256-kb (256 k 1) static ram document number: 001-06447 rev. ecn no. issue date orig. of change description of change ** 901742 see ecn nxr new data sheet *a 2892510 03/18/2010 vkn removed 12ns speed bin updated ordering information table updated package diagrams added sales, solutions, and legal information *b 3108898 12/13/2010 aju added ordering code definitions . *c 3217480 04/06/2011 pras added acronyms and units of measure . updated in new template. [+] feedback
document #: 001-06447 rev. *c revised april 6, 2011 page 13 of 13 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c197bn ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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